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B. Tech - III(EC), Semester - VI L T P C  
EC 304: DIGITAL INTEGRATED CIRCUITS(NEW) 3 0 2 4  
COURSE OUTCOME:
  • To be able to learn BJT logic families.
  • To be able to design inverter with NMOS logic and CMOS logic with required noise margin and delay specifications.
  • To be able to learn Layout.
  • To be able to get idea about different semiconductor Memories.
SYLLABUS:
• BJT MODELING AND LOGIC FAMILIES
(10 Hours)
Modeling Of P-N Junction Diode And BJT, Diode And BJT Model Parameter Extraction, Schottky Transistor, BJT Inverter, DC Switching Characteristic, Introduction to RTL, DTL TTL, Schottky TTL, I2L and ECL Logic Family, Concept of Noise margin, Fan Out and Propagation Delay, Basic BiCMOS Circuits: Static Behavior, Switching Delay in BiCMOS Logic Circuits.
• MOS TRANSISTOR
(06 Hours)
MOS Structure And Operation, MOSFET Structure And Operations, MOSFET Current- Voltage Characteristics, Channel Length Modulation, Substrate Bias Effect, MOSFET Capacitances, MOSFET Model.
• NMOS LOGIC DESIGN
(05 Hours)
Resistive-Load Inverter, Saturated-Loaded Inverter, Linear Loaded Inverter, Depletion Loaded Inverter, Graphical Determination Of VTC, Calculation Of VTC Critical Points, Power Dissipation And Rise Time - Fall Time, NMOS Logic Gates.
• CMOS LOGIC DESIGN
(04 Hours)
CMOS Inverter Technology, Static Characteristics, Dynamic Behavior, Static And Dynamic Power Dissipation, Power-Delay Product. CMOS Gates, TTL-CMOS Interfacing.
• PROCESSING TECHNOLOGY
(06 Hours)
Fabrication Process Flow, CMOS N-Well Process, Layout Design Rules, Full-Custom Mask Layout Design, Stick Diagram.
• INTRODUCTION OF FPGA ARCHITECTURE
(03 Hours)
 
• SEMICONDUCTOR MEMORIES
(06 Hours)
Type Of Memories, Implementation Of ROMs, MOS ROM Cells, MOS EPROM and EEPROM Applications, Static and Dynamic Read - Write Memories, Organization Of RAM, Paralleling Of Semiconductor Memory Integrated Circuit Chips.
(Total Contact Time:42 Hours)
PRACTICALS
01) Introduction to SPICE Circuit Simulator.
02) Realization Of NOR Gate Using RTL Logic. Obtain & Plot its Transfer Characteristics And Determine Noise Margins, Fan-Out and Propagation Delay.
03) Realization of NAND Gate Using TTL Logic. Obtain & Plot Its Transfer Characteristic And Determine Noise margins, Fan-out and Propagation Delay.
04) Realization Of Wired NAND Gate Using DTL and MDTL Logic. Obtain & Plot Its Transfer Characteristic And Determine Noise margins, Fan-out and Propagation Delay.
05) Implementation of NMOS Inverter, Obtain & Plot Its Transfer Characteristics And Determine Noise margins And Measure Propagation Delay.
06) Implementation of CMOS Inverter. Obtain & Plot Its Transfer Characteristics, Determine Noise Margins and Measure Propagation Delay.
07) Realization of MOSFET Characteristics Using Circuit Simulator Characteristics and BSIM Models.
08) Realization Of Inverter Gate Using BiCMOS Logic, Obtain & Plot Its Transfer Characteristics, Determine Noise Margins.
09) Realization Of CMOS Static & Dynamic Characteristics Using Circuit Simulator Characteristics And BSIM Models.
10) Design And Implementation of TTL-CMOS & CMOS-TTL Interfacing.
11) Design And Implement of 1-Bit RAM CELL Using JK & SR Flip-Flop.
12) Layout of CMOS Inverter And Parasitic Extraction and Obtain VTC of Extracted Net List.
BOOKS RECOMMENDED
1. Taub H. and Schilling D., "Digital Integrated Electronics", McGraw-Hill, International Ed., 2008.
2. Sung-Mo Kang and Leblebici Y., "CMOS Digital Integrated Circuits: Analysis And Design", Tata McGraw-Hill; 3rd Ed., 2003.
3. Rabaey Jan, Chandrakasan Anantha Nikolic, "Digital Integrated Circuits: A Design Perspective", Pearson Education, 2nd Ed., 2nd Impression, 2008.
4. Hodges D. A. and Jackson H. G. "Analysis And Design Of Digital Integrated Circuits", 3rd Ed., McGraw-Hill, 2004.
5. Baker R. J., Li H. W. and Boyce D. E., "CMOS Circuits Design Layout and Simulation", PHI 2nd 2005.